GaNFast power ICs with GaNSense technology integrate critical, real-time, autonomous sensing and protection circuits which further improve Navitas’ industry-leading reliability and robustness. This technology also enables a patent-pending, loss-less current-sensing capability, which improves energy savings by up to an additional 10% compared to prior generations, as well as further reducing external component count and shrinking system footprints.
Fsw < 100kHz
External gate drive
Integrated Gate Drive
2KV ESD rating
GaNFast benefits plus:
Loss-less Current Sensing
Loss-less Current Sensing
When measuring current in a circuit, a foreign sense element is inserted into the system for measurement. Most existing approaches require careful tradeoffs. Some motor applications even push to move toward complicated “sensorless” control to save that appreciable sensor cost and PCB space – and be able to operate in a wide ambient temperature environment or challenging ionization/magnetic field environment. These approaches still face challenges in timing, delays, and accuracy operating from software models and complicated control-loop algorithms. Navitas’ new current-sense feature offers a highly integrated, “lossless”, and localized approach to solve many of those challenges.
With a variety of applications and requirements comes a variety of current-sensing approaches to meet the design goals in the most cost-effective and size-efficient manner. With the advent of a near-ideal, lossless “GaNSense” current sensing, fully-integrated with the power device that is fast, accurate, and can serve the critical functions of both control and protection with effectively zero size and cost impact.
Table 1. Summary of common current-sensing methods and their performance
Loss-less current Sensing
Navitas’ GaNSense family offers loss-less current sensing integrated in the IC, removing the shunt current-sense resistor and its associated headaches, such as improving the overall efficiency of the system with lower total series resistance, while also increasing robustness with fast, internal, 30-100ns short-circuit protection.
This is a “localized” approach, which is senses and acts upon locally to the current and power elements of interest. Localized control and response time allows this method to be fast and effective, while also minimizing corruption of the control signals from system noise, long traces, etc. compared to other methods. In this way, it becomes possible to use this method not only for over-current failsafe and short-circuit protection, but also cycle-by-cycle current limit and current-mode control and regulation.
This self-governing power block may indeed represent the future of powerstage sensing and protection, allowing for higher reliability, pushing the limits of performance, and freeing the main system controller to focus on more complicated control algorithms and responsibilities.
Over-Current Protection (OCP)
6x faster protection – detect to protect in 30ns!
The GaNSense technology offers cycle-by-cycle over-current detection and protection (OCP) circuitry to protect the GaN IC against high current levels. During the on-time of each switching cycle, should the peak current exceed the desired limit, then the internal gate drive will turn the GaN IC off quickly and truncate the on-time period to prevent damage from occurring to the IC.
Compared to discrete solutions, GaNFast ICs with GaNSense technology can respond 6x faster and remove all the associated external components, layout issues, and slow response time.
Discrete FET Solution
Discrete solution using QR controller OCP function
- Existing solutions use ext. RCS
- Filter + controller delay slow
- Over Current Protection DCM Timing
- Cycle by cycle over current protection in CCM boost configuration
Over-Temperature Protection (OTP)
Over-temperature detection and protection (OTP) circuitry is integrated into the IC to protect against excessively high junction temperatures (TJ). High junction temperatures can occur due to overload, high ambient temperatures, and/or poor thermal management. Should TJ exceed the internal TOTP+ threshold then the IC will latch off safely. When TJ decreases again and falls below the internal TOTP- threshold, then the OTP latch will be reset. Until then, internal OTP latch is guaranteed to remain in the correct state.