Navitas Semiconductor - World's First & Fastest GaN Power IC
Navitas Semiconductor - World's First & Fastest GaN Power IC

Application Note AN020

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Thermal Simulation Model for Selection of QFN 5×6, QFN 6×8 and QFN 8×8 Package Types

By Tom Ribarich, Sr. Director Strategic Marketing, and Bin Li, Director of Applications

Introduction

Designing a high-frequency and high-density power supply for a specific application and meeting all electrical, mechanical and thermal requirements can be a very challenging task. Part of fulfilling the thermal requirements involves ensuring that the GaN power FET junction temperature (TJ) does not exceed the recommended maximum rating during all line and load conditions, and also keeping the maximum plastic case touch temperature below its maximum allowable level. Selecting the correct QFN package type and RDS(ON)value can be a challenge in itself due to the large portfolio of products available and difficulty in predicting the final system temperatures.

This application note includes a detailed thermal setup and simulations for different power levels for QFN 5×6, QFN 6×8 and QFN 8×8 package types based on top- and bottom-cooled thermal management solutions. The results of these simulations include estimated device junction temperatures (TJ) for different device power loss (PLOSS) values. This model will help guide designers to select the correct RDS(ON) value and QFN package type for their application based on cooling method, device power loss, and resulting device junction temperature (TJ).

Overview

The QFN 5×6, QFN 6×8 and QFN 8×8 package types each have their own unique package dimensions, surface areas, and cooling pad sizes. These all have an effect on the final GaN device junction temperature (TJ) for a given device PLOSS, and cooling method. For top-cooling, the package top side surface area will affect how well the heat can flow from the die upward to the thermal interface material (TIM). For bottom-cooling, the pad size and PCB thermal vias will affect how well the heat can flow from the die downward to the PCB board. These different parameters and cooling methods need to be analyzed further and thermally simulated so we can compare the thermal performance of each package type and help guide designers to more easily select the correct package for their application and thermal requirements.

Figure 1: QFN 5×6, QFN 6×8, QFN 8×8 package types

PCB Layouts

2-layer PCB layouts were created for each package type under similar PCB size and copper area conditions (Figure 2). The IC components for each GaN Power IC are included in the layouts since these affect how the heat can flows away from the package in each direction. The components are placed on the top layer and connected with top layer traces (no vias). The remainder of the top side area is filled up with copper (red). The bottom layer copper fills up the complete PCB area on the bottom side. Thermal vias are then placed inside the pad area of each IC, and the heat flows from the pad down to the PCB to the top and bottom layers.

Figure 2: Schematic and PCB layouts used for thermal simulations

Thermal Model Stack-Up (Top-Cooled)

The top-cooled thermal model stack-up includes the GaN Power IC QFN mounted on the top side of a FR4 PCB (Figure 3). The heat due to the device power loss thermally conducts from the internal GaN power FET, up through the QFN plastic package, through the TIM and Mylar materials, through the copper shielding, and to the plastic case. The heat then thermally convects from the top surface of the plastic case to the surrounding ambient air. Heat also flows from the device downward to the PCB, and spreads laterally to the sides and then upward through the same materials to the plastic case. So multiple parallel paths of heat flow towards the top side are formed. The bottom area below the PCB is the inside of the power supply unit and it heats up to very high temperature that limits heat flow in the downward direction.

Figure 3: Thermal stack-up for top-side cooling method

Figure 4: Thermal conductivity summary table for top side cooling materials

Thermal Simulation Setup (Top-Cooled)

The top-cooled simulation setup (Figure 4) includes the device and stack-up of materials with additional boundary conditions of 85℃ (fixed) for the other three edges of the closed power supply system. This internal ambient air will increase to high temperatures during the simulation and limit thermal conduction in the downward direction (similar to actual power supply design with power components placed on opposite side of PCB from the device). The closed power supply system is then placed into a larger closed system with the ambient air temperature set at 25℃. This setup is very similar to the thermal testing method of an actual power supply unit on the bench inside an enclosed chamber.

Figure 4: Thermal simulation setup diagrams for top cooling method

Thermal Simulation Results (Top-Cooled)

Top-cooled thermal simulations were run for each package type at 0.5 W, 1 W, and 1.5 W PLOSS conditions, and the target plastic case surface temperature was set at 70℃. The data was then plotted for PLOSS vs TJ, and for each package type (Figure 5). From these curves, the designer can estimate the device TJ temperature for a given PLOSS and package type. At lower PLOSS values (0.5 W) there is a small difference in device TJ temperature between the package types. As PLOSS increases above 1 W, the TJ difference becomes larger. The difference in PLOSS versus TJ for each package type can be used in two ways. For a given TJ(MAX) (i.e., 120℃), QFN 8×8 will allow 7% more PLOSS compared to QFN 5×6, or, for a given PLOSS (i.e., 1.28 W), QFN 8×8 will reduce Tj by about 4 deg C compared to QFN 5×6. Depending on the PLOSS for the application and the TJ(MAX) target, increasing the package size can help give additional design margin for tolerances.
Figure 5: Top-cooled thermal simulation data & curves (PLOSS vs TJ) for different package types

Thermal Model Stack-Up (Bottom-Cooled)

The bottom-cooled thermal model stack-up includes the GaN Power IC QFN mounted on the top side of a FR4 PCB (Figure 6). The heat due to the device power loss thermally conducts from the internal GaN power FET, down through the QFN leadframe, through the PCB and vias, through TIM and Mylar materials, through the copper shielding, and to the plastic case. The heat then thermally convects from the bottom surface of the plastic case to the surrounding ambient air. The top area above the QFN is the inside of the power supply unit and it heats up to very high temperature that limits heat flow in the upward direction.

Figure 6: Thermal stack-up for bottom-side cooling method

Figure 7: Thermal conductivity summary table for bottom side cooling materials

Thermal Simulation Setup (Bottom-Cooled)

The bottom-cooled simulation setup (Figure 8) includes the device and stack-up of materials with additional boundary conditions of 85℃ (fixed) for the other three edges of the closed power supply system. This internal ambient air will increase to high temperatures during the simulation and limit thermal conduction in the upward direction (similar to actual power supply design with power components placed on opposite side of PCB from the device). The closed power supply system is then placed into a larger closed system with the ambient air temperature set at 25℃. This setup is very similar to the thermal testing method of an actual power supply unit on the bench inside an enclosed chamber.

Figure 8: Thermal simulation setup diagrams for bottom cooling method

Thermal Simulation Results (Bottom-Cooled)

Bottom-cooled thermal simulations were run for each package type at different PLOSS values, and again with the target plastic case surface temperature set at 70℃ (figure 9). From these curves, the designer can also estimate the device TJ temperature for a given PLOSS and package type. With bottom side cooling, the TJ temperatures are about 3℃ lower than compared with top side cooling, for the same PLOSS value (i.e., 1.35 W). The same trade-off as top-cooled also exists for bottom-cooled for the different package types. When increasing the package size from QFN 5×6 to QFN 8×8, the designer can increase the PLOSS budget for a given TJ, or reduce TJ for a given PLOSS.
Figure 9: Bottom-cooled thermal simulation curves (PLOSS vs TJ) for different package types

RDS(ON) and Package Type Selection

A typical 65 W HFQR Flyback circuit will have 1.5 ARMS current flowing in the primary side switch at 90 VAC and 100% output load. The PLOSS values at this 1.5 Arms condition are calculated for different RDS(ON) values (Table 1), and the corresponding TJ values for top and bottom cooling methods are obtained from the thermal simulation graphs (Figure 10). From the summary table, the designer can select from different RDS(ON) values and package types, depending on PLOSS, TJ, and preferred cooling method. From the data, RDS(ON) = 260mΩ gives high TJ values close to or greater than 115℃ for all top-cooled options, as well as bottom-cooled QFN 5×6. RDS(ON) = 170m gives very low TJ values close to 100℃ for all cooling methods and package types. RDS(ON)= 210mΩ looks like a reasonable selection due to TJ values below 110℃ for all cooling methods and package types (which allows for good TJ margin away from a Tj-max = 120℃). The designer can further optimize for package type selection based on cooling method and PCB footprint area.

Figure 10: Top-cooling (left) and bottom-cooling (right) thermal simulation curves

Table 1: ISWITCH, PLOSS, and TJ estimates for different RDS(ON) values (65 W HFQR Flyback Circuit, 90 VAC/100%)

Conclusions

These thermal simulations are intended to be used as a guide for designers to estimate the TJ and help select the correct RDS(ON) and package type for a given PLOSS and cooling method. The TJ temperature differences between the different package types are typically between 3-5℃ at PLOSS values above 1 W, and these differences can help greatly when designing a power supply for worst case conditions and design margin is required. The thermal simulations have also shown that these differences can allow for higher RDS(ON) values to be used (in a larger package), especially if bottom-cooling method is used. Final results with actual power supply measurements may vary depending on the final materials used in the thermal stack-up and their thermal conductivity values.

References (www.navitassemi.com)

1) Thermal Management of GaNFast Power ICs, AN010, Navitas Semiconductor, 2019

2) Thermal Management of GaNFast NV612x Power IC, AN011, Navitas Semiconductor, 2019

3) GaNFast NV613x/NV615x, NV6169 Power ICs with GaNSense Technology datasheets, Navitas Semiconductor, 2021/2022

Additional Information

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